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s3c72k8/p72k8 product overview 1- 1 1 product overview overview the s3c72k8 singl-chip cmos microcontroller has been designed for high performance using samsung's newest 4-bit cpu core, sam48 ( samsung arrageable microcontrollers). with a two-channel comparator, up-to- 320-dot lcd direct drive capability, 8-bit timer/counter, watchdog timer and serial i/o, the s3c72k8 offers an excellent design solution for a wide variety of applications which require lcd functions. up to 27 pins of the 80-pin qfp package can be dedicated to i/o. seven vectored interrupts provide fast response to internal and external events. in addition, the s3c72k8's advanced cmos technology provides for low power consumption and a wide operating voltage range. otp the s3c72k8 microcontroller is also available is otp (one time programmable) version, S3P72K8. S3P72K8 microcontroller has an one-chop 8 kbyte one time programmable eprom instead of masked rom. the S3P72K8 is comparable to s3c72k8, both in function and in pin configuration.
product overview s3c72k8/p72k8 1- 2 features memory ? 8 k 8 -bit ram ? 1,024 4 -bit rom 27 i/o pins ? input only: 4 pins ? i/o: 15 pins ? output: maximum 8 pins for 1-bit level output (sharing with segment driver outputs) comparator ? two channel mode: internal reference (4-bit resolution) ? one channel mode: external reference lcd controller/driver ? 40 segments and 8 common terminals ? 3, 4 and 8 common selectable ? internal resistor circuit for lcd bias ? all dot can be switched on/off 8-bit basic timer ? 4 interval timer functions ? watchdog timer 8-bit timer/counter ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider ? serial i/o interface clock generator 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive only mode ? lsb-first or msb-first transmission selectable ? internal or external clock source bit sequential carrier ? support 16-bit serial data transfer in arbitrary format watch timer ? timer interval generation: 0.5 s, 3.9 ms at 32,768 hz ? four frequency outputs to buz pin ? clock source generation for lcd interrupts ? three internal vectored interrupts : intb, intt0, ints ? four external vectored interrupts : int0, int1, int4, intk ? two quasi-interrupts : int2, intw memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system oscillation stops) ? subsystem clock stop mode oscillation sources ? crystal, ceramic, or external rc for system clock ? main system clock frequency: 0.4 mhz ?6 mhz ? subsystem clock frequency: 32 , 768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.67 us at 6 mhz (minimum) ? 0.95 m s at 4.19 mhz (minimum) ? 122 m s at 32, 768 khz (minimum) operating temperature ? ? 40 c to 85 c operating voltage range ? 2.0 v to 5.5 v package type ? 80 -pin qfp
s3c72k8/p72k8 product overview 1- 3 block diagram program status word arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block stack pointer clock 8 kbyte program memory 1024 x 4-bit data memory x in xt in program counter flags p0.0/sck/k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 x out xt out watchdog timer input port 1 comparator i/o port 0 watch timer basic timer sio p1.0/int0/cin0 p1.1/int1/cin1 p1.2/int2 p1.3/int4 lcd driver/ controller i/o port 4 8-bit timer/ counter i/o port 2 i/o port 3 v lc1 -v lc5 com0-com7 seg0-seg31 p5.0/seg32- p5.7/seg39 p2.0-p2.3 p3.0 p3.1 p3.2/lcdsy p3.3/cldck p4.0/clo p4.1/tcl0 p4.2/tclo0 figure 1 -1 . s3c72k8 simplified block diagram
product overview s3c72k8/p72k8 1- 4 pin assignments s3c72k8 (80-qfp-1420c) p5.6/seg38 p5.7/seg39 v lc1 v lc2 v lc3 v lc4 v lc5 p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 v dd v ss x out x in test xt in xt out reset p1.0/int0/cin0 p1.1/int1/cin1 p1.2/int2 p1.3/int4 p2.0 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 com5 com4 com3 com2 com1 com0 tclo0/p4.2 tcl0/p4.1 clo/p4.0 lcdck/p3.3 lcdsy/p3.2 p3.1 p3.0 p2.3 p2.2 p2.1 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32/p5.0 seg33/p5.1 seg34/p5.2 seg35/p5.3 seg36/p5.4 seg37/p5.5 figure 1 -2 . s3c72k8 80- qfp pin assignment
s3c72k8/p72k8 product overview 1- 5 pin descriptions table 1 - 1. s3c72k8 pin descriptions pin name pin type description circuit type pin number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is pos sible. individual pins are software configurable as input or output. individual pins are software configurable as open- drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. e?2 8 9 10 11 k0/ sck k1/so k2/si k3/buz p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit or 4-bit read and test are possible. the 1-bit unit pull-up resistors are assigned to input pins by software. an interrupt is generated by digital input at p1.0, p1.1. f?4 f?4 a?3 a?3 20 21 22 23 int0/cin0 int1/cin1 int2 int4 p2.0?p2.3 i/o same as port 0 except that 8-bit read/write and test is possible. e?2 24?27 ? p3.0 p3.1 p3.2 p3.3 28 29 30 31 ? ? lcdsy lcdck p4.0 p4.1 p4.2 i/o same as port 0 except that port 4 is 3-bit i/o port. e?2 32 33 34 clo tcl0 tclo0 p5.0?p5.7 o output port for 1-bit data h?11 75? 80,1,2 seg32? seg39 sck i/o serial i/o interface clock signal e?2 8 p0.0/k0 so i/o serial data output e?2 9 p0.1/k1 si i/o serial data input e?2 10 p0.2/k2 buz i/o 2 khz, 4 khz, 8 khz or 16 khz frequency output at the watch timer clock frequency of 32.768 khz. e?2 11 p0.3/k3 k0?k3 i/o external interrupt. the triggering edge is selectable. e?2 8?11 p0.0?p0.3 int0 int1 i external interrupts. the triggering edge for int0 and int1 is selectable. f?4 20 21 p1.0/cin0 p1.1/cin1 int2 i quasi-interrupt with detection of rising or falling edges a?3 22 p1.2 int4 i external interrupts with detection of rising and falling edges a?3 23 p1.3
product overview s3c72k8/p72k8 1- 6 table 1 - 1. s3c72k8 pin descriptions (continued) pin name pin type description circuit type pin number share pin cin0 cin1 i 2-channel comparator input. cin0: comparator input or external reference input cin1: compara tor input only. f?4 20 21 p1.0/int0 p1.1/int1 lcdsy i/o lcd synchronization clock output for display expansion e?2 30 p3.2 lcdck i/o lcd clock output for display expansion e?2 31 p3.3 clo i/o clock output e?2 32 p4.0 tcl0 i/o external clock input for timer/counter 0 e?2 33 p4.1 tclo0 i/o timer/counter 0 clock output e?2 34 p4.2 seg32? seg39 o lcd segment signal output h?11 75? 80,1,2 p5.0?p5.7 seg0? seg31 o lcd segment signal output h?6 43?74 ? com0? com7 o lcd common signal output h?6 35?42 ? v lc1 ?v lc5 ? lcd power supply. voltage dividing resistors are assignable by mask option. ? 3?7 ? x in , x out ? crystal, ceramic or rc oscillator pins for system clock. ? 15, 14 ? xt in , xt out ? crystal oscillator pins for subsystem clock. ? 17, 18 ? v dd ? main power supply ? 12 ? v ss ? ground ? 13 ? reset i chip reset signal input b 19 ? test i chip test signal input (must be connected to v ss ) ? 16 ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode
s3c72k8/p72k8 product overview 1- 7 pin circuit diagrams p-channel n-channel in v dd figure 1 -3 . pin circuit type a in v dd pull-up resistor enable p-channel pull-up resistor schmitt trigger figure 1 -4 . pin circuit type a-3 schmitt trigger in v dd pull-up resistor figure 1 -5 . pin circuit type b p-channel n-channel v dd out output disable data figure 1 -6 . pin circuit type 7
product overview s3c72k8/p72k8 1- 8 schmitt trigger n-ch v dd resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1-7. pin circuit type e-2 i/o schmitt trigger resistor enable v dd pull-up resistor + - ext-ref (p1.0 only) analog in digital in comparator int-ref digital or analog selectable by software (p1mod) figure 1-8. pin circuit type f-4
s3c72k8/p72k8 product overview 1- 9 out v lc3 seg/com data v lc2 output disable v dd v lc1 v lc4 v lc5 figure 1-9. pin circuit type h-5
product overview s3c72k8/p72k8 1- 10 out seg/com v lc1 v lc2 v dd v lc4 v lc3 v lc5 figure 1-10. pin circuit type h-6 p-ch n-ch v dd out output disable 1 data circuit type h-5 n-ch seg output disable 2 figure 1-11. pin circuit type h-11
s3c72k8/p72k8 electrical data 15- 1 1 5 electrical data overview in this section, information on s3c72k8 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abso lute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? comparator electrical characteristics ? a.c. electrical characteristics ? o perating voltage range stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request miscellaneous timing waveforms ? a .c timing measurement point s ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset signal ? input timing for external interrupts ? serial data transfer timing
electrical data s3c72k8/p72k8 15- 2 table 15- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i 1 all i/o pins active ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o pins active ? 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) all i/o port, total + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty .
s3c72k8/p72k8 electrical data 15- 3 table 15- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units input high voltage v ih1 ports 2, 3, p4.0 and p4.2 0.7 v dd ? v dd v v ih2 ports 0, 1, p4.1 and reset 0.8 v dd v dd v ih3 x in , x out and xt in v dd ? 0. 1 v dd input low voltage v il1 ports 2, 3, p4.0 and p4.2 ? ? 0.3 v dd v v il2 ports 0, 1, p4.1 and reset 0.2 v dd v il3 x in , x out and xt in 0. 1 output high voltage v oh 1 v dd = 4.5 v to 5.5 v i oh = ? 3 m a ports 0, 2 , 3 and 4 v dd ? 2.0 v dd ? 0.4 ? v v oh 2 v dd = 4.5 v to 5.5 v i oh = ? 100 m a ports 5 v dd ? 2.0 ? ? output low voltage v ol 1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 0, 2 , 3 and 4 ? 0.4 2 v v ol 2 v dd = 4.5 v to 5.5 v i oh = ? 100 m a ports 5 ? ? 1 input high leakage current i lih1 v i n = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v i n = v dd x in , x out and xt in 20 input low leakage current i lil1 v i n = 0 v all input pins except x in , x out , xt in , and reset ? ? ? 3 m a i lil2 v i n = 0 v x in , x out and xt in ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 m a
electrical data s3c72k8/p72k8 15- 4 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units pull-up resistor r l i v i n = 0 v; v dd = 5 v 10 % port s 0 -4 15 40 80 k w v dd = 3 v 10 % 30 80 200 r l 2 v i n = 0 v; v dd = 5 v 10 % reset 150 220 350 v dd = 3 v 10 % 300 400 800 lcd voltage dividing resistor r lcd ? 40 60 90 k w | v dd -com i | voltage drop (i = 0 -7 ) v dc v dd = 2.7 v to 5.5 v ? 15 m a per common pin ? ? 120 mv | v dd -segx| voltage drop (x = 0 -39 ) v ds v dd = 2.7 v to 5.5 v ? 15 m a per segment pin ? ? 120 v lc 1 output voltage v lc 2 v dd = 2.0 v to 5.5 v (1) lcd clock = 0 hz, v lc 5 = 0 v 0.8 v dd ? 0.2 0.8 v dd 0.8 v dd + 0.2 v v lc 2 output voltage v lc 3 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v lc 3 output voltage v lc 4 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc 4 output voltage v lc 5 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2
s3c72k8/p72k8 electrical data 15- 5 table 15- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units supply current ( 1 ) i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 3.5 2.5 8.0 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.8 1.3 4.0 3.0 i dd2 ( 2 ) idle mode v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.4 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 ma i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1 . currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents, comparator. 2 . data includes power consumption for subsy stem clock oscillation. 3 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b".
electrical data s3c72k8/p72k8 15- 6 table 15- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 4.5 v to 5.5 v ? ? 10 ms v dd = 2.7 v to 4 .5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency r = 10 k w , v dd = 5 v ? 2 ? mhz r = 30 k w , v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in i nput frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
s3c72k8/p72k8 electrical data 15- 7 table 15- 4. subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 2.0 v to 4 .5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs.
electrical data s3c72k8/p72k8 15- 8 table 15- 5. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 15-6 . comparator electrical characteristics (t a = ? 40 c + 85 c, v dd = 4.0 v to 5.5 v ) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref 0 v dd v input voltage accuracy v cin ? 150 mv input leakage current i cin , i ref ? 3 3 m a
s3c72k8/p72k8 electrical data 15- 9 table 15-7 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s v dd = 2.0 v to 5 .5 v 0.95 ? 64 with subsystem clock (fxt) 114 122 125 tcl0 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 2.0 v to 5 .5 v 1 tcl0 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 2.0 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 650 v dd = 2.0 v to 5 .5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v external sck source 325 ? ? ns internal sck source t kcy /2 ? 50 v dd = 2.0 v to 5 .5 v external sck source 1600 internal sck source t kcy / 2 ? 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 2.0 v to 5 .5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 2.0 v to 5 .5 v external sck source 600 internal sck source 500 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
electrical data s3c72k8/p72k8 15- 10 table 15-7 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units output delay for sck to so t kso v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 2.0 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 , int1, int2, int4, k0? k3 10 ? ? m s reset input low width t rsl input 10 ? ? m s 1.5 mhz cpu clock 1.05 mhz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 2.0 v 2.7 v figure 15- 1. standard operating voltage range
s3c72k8/p72k8 electrical data 15- 11 table 15-8. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.0 ? 5.5 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
electrical data s3c72k8/p72k8 15- 12 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 15-2. stop mode release timing when initiated by reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 15-3. stop mode release timing when initiated by interrupt request
s3c72k8/p72k8 electrical data 15- 13 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 15-4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 15-5 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 15-6 . clock timing measurement at xt in
electrical data s3c72k8/p72k8 15- 14 tcl0 t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 15-7 . tc l timing reset t rsl 0.2 v dd figure 15-8 . input timing for reset reset signal int0, 1, 2, 4, k0 to k3 t inth t intl 0.8 v dd 0.2 v dd figure 15-9 . input timing for external interrupts and quasi-interrupts
s3c72k8/p72k8 electrical data 15- 15 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 15- 1 0 . serial data transfer timing
s3c72k8/p72k8 mecha nical data 16- 1 16 mechanical data overview the s3c72k8 microcontroller is currently available in a 80-pin qfp package. 80-qfp-1420c #80 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 0.80 0.35 + 0.10 note : dimensions are in millimeters. 0.15 max (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 figure 16-1. 80-qfp-1420c package dimensions
s3c72k8/p72k8 S3P72K8 otp 17- 1 17 S3P72K8 otp overview the S3P72K8 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c72k8 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P72K8 is fully compatible with the s3c72k8, both in function and in pin configuration except rom size. because of its simple programming requirements, the S3P72K8 is ideal for use as an evaluation chip for the s3c72k8.
S3P72K8 otp s3c72k8 /p72k8 17- 2 S3P72K8 (80-qfp-1420c) p5.6/seg38 p5.7/seg39 v lc1 v lc2 v lc3 v lc4 v lc5 p0.0/ sck /k0 p0.1/so/k1 sdat /p0.2/si/k2 sclk /p0.3/buz/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset p1.0/int0/cin0 p1.1/int1/cin1 p1.1/int2 p1.3/int4 p2.0 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 com5 com4 com3 com2 com1 com0 tclo0/p4.2 tcl0/p4.1 clo/p4.0 lcdck/p3.3 lcdsy/p3.2 p3.1 p3.0 p2.3 p2.2 p2.1 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32/p5.0 seg33/p5.1 seg34/p5.2 seg35/p5.3 seg36/p5.4 seg37/p5.5 figure 17-1. S3P72K8 pin assignments (80-qfp package)
s3c72k8/p72k8 S3P72K8 otp 17- 3 table 17-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.2 sdat 10 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p0.3 sclk 11 i serial clock pin. input only pin. test v pp 16 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 19 i chip initialization v dd /v ss v dd /v ss 12/13 i logic power supply pin. v dd should be tied to +5 v during programming. table 17-2. comparison of S3P72K8 and s3c72k8 features characteristic S3P72K8 s3c72k8 program memory 8-kbyte eprom 8-kbyte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5v pin configuration 80 qfp 80 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P72K8, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 17-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P72K8 otp s3c72k8 /p72k8 17- 4 notes

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